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| Ordering number : ENN6871A CMOS IC LC72714W Mobile FM Multiplex Broadcast IC with On-Chip VICS Decoder Overview The LC72714W is data demodulator ICs for receiving FM multiplex broadcasts for mobile reception in the DARC format. This IC includes an on-chip bandpass filter for extracting the DARC signal from the FM baseband signal. It also integrates a decoder circuit that performs the VICS data processing on the same chip and can implement a compact, multifunction VICS reception system. The LC72714W is an improved version of the LC72710W that features circuit improvements that allow a single tuner to receive both the VICS data and the dGPS data supported by the earlier device. Note that a contract with VICS Center is required to evaluate this sample IC and to produce end products that support VICS. * 7.2 MHz crystal oscillator circuit * Two power saving modes: STNBY and EC STOP * Dedicated frame synchronization circuit for simultaneous reception of dGPS and VICS data * Applications can use either a parallel CPU interface (DMA) or a CCB serial interface. * Supply voltage: 2.7 to 3.6 V Package Dimensions unit: mm 3190-SQFP64 [LC72714W] 12.0 10.0 1.25 48 49 Functions * * * * * * * * Adjustment-free 76 kHz SCF bandpass filter Built-in VICS decoder MSK delay detection system based on a 1T delay. Error correction function based on a 2T delay (in the MSK detection stage) Digital PLL based clock regeneration function Shift-register 1T and 2T delay circuits Block and frame synchronization detection circuits Functions for setting the number of allowable BIC errors and the number of synchronization protection operations. Error correction using (272, 190) codes Built-in layer 4 CRC code checking circuit On-chip frame memory and memory control circuit for vertical correction 0.5 0.18 1.25 33 32 0.15 12.0 10.0 0.5 1.25 64 17 1 16 * * * 0.5 SANYO: SQFP64 * CCB is a trademark of SANYO ELECTRIC CO., LTD. * CCB is SANYO's original bus format and all the bus addresses are controlled by SANYO. Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Company TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 92001TN (OT) No. 6871-1/29 0.1 0.5 1.7max 1.25 LC72714W Specifications Absolute Maximum Ratings at Ta = 25C, VSS = 0 V Parameter Maximum supply voltage Input voltage Symbol VDD VIN(1) VIN(2) VOUT(1) VOUT(2) IOUT(1) IOUT(2) ITTL Pdmax Topr Tstg A0/CL, A1/CE, A2/DI, RST, STNBY Pins other than VIN(1) DO Pins other than VOUT(1) INT, RDY, DREQ, and D0 to D15 Pins other than IOUT(1) Total for all the output pins Ta 85C Conditions Ratings -0.3 to +5.5 -0.3 to +7.0 -0.3 to VDD + 0.3 -0.3 to +7.0 -0.3 to VDD + 0.3 0 to 4.0 0 to 2.0 20 200 -40 to +85 -55 to +125 Unit V V V V V mA mA mA mW C C Output voltage Output current Allowable output current (total) Allowable power dissipation Operating temperature Storage temperature Allowable Operating Ranges at Ta = -40 to +85C, VSS = 0 V Parameter Supply voltage High-level input voltage Symbol VDD VIH1 VIH2 VIL1 VIL2 FOSC VXI VMPX Input amplitude VMPX2 Clock low-level period Clock high-level period Data setup time Serial I/O Data hold time CE wait time CE setup time CE hold time Data latch change time Data output time CRC4 change time tCL tCH tSU tHD tEL tES tEH tLC tDDO tCRC A0/CL, A1/CE, A2/DI, RST, STNBY DACK, WR, RD, CS, SP, BUSWD, A3, IOCNT1, IOCNT2 Pins for which VIH1 applies Pins for which VIH2 applies This IC operates with a frequency precision of 250 ppm With a sine wave input to XIN, capacitor coupling, VDD = +2.7 to +3.6 V With a 100% modulated composite signal input to MPXIN, VDD = +3.3 V With a 100% modulated composite signal input to MPXIN, VDD = +2.7 V A0/CL A0/CL A0/CL, A2/DI A0/CL, A2/DI A0/CL, A1/CE A0/CL, A1/CE A0/CL, A1/CE A1/CE DO, A0/CL CRC4, A0/CL 277 400 120 120 0.7 0.7 0.7 0.7 0.7 0.7 0.7 0.7 555 0.7 Conditions Ratings min 2.7 0.7 VDD 0.7 VDD VSS VSS 7.2 900 500 450 typ max 3.6 5.5 VDD 0.3 VDD 0.3 VDD Unit V V V V V MHz mVrms mVrms mVrms s s s s s s s s ns s Low-level input voltage Oscillator frequency XIN input sensitivity No. 6871-2/29 LC72714W Allowable Operating Ranges: Parallel Interface at Ta = -40 to +85C, VSS = 0 V Parameter Address to RD setup RD to address hold RD low-level width RD low-level width (when RDY is used) RD cycle wait RDY width (Register read) RD data hold Address to WR setup WR to address hold Parallel I/O WR cycle wait WR low-level width WR data hold RDY output delay Corrected output RD width Corrected output RD width (when RDY is used) RDY width (corrected output read) DACK to DREQ delay DMA cycle wait RD low-level width (DMA) Notes: Symbol tSARD tHARD tWRDL1 tWRDL2 tCYRD tWRDY tRDH tSAWR tHAWR tCYWR tWWRL tWDH tDRDY tWDRD1 tWDRD2 tWDRDY tDREQ tCYDM tWRDM Conditions A0/CL, A1/CE, A2/DI, A3, RD A0/CL, A1/CE, A2/DI, A3, RD, tWRDL=>250 ns RD RD A0/CL, A1/CE, A2/DI, A3, RD RDY RD, DATn A0/CL, A1/CE, A2/DI, A3, WR A0/CL, A1/CE, A2/DI, A3, WR A0/CL, A1/CE, A2/DI, A3, WR WR WR, DATn RD, RDY RD (BUSWD = L 8 bits) RD (BUSWD = H 16 bits) RD (BUSWD = L 8 bits) RD (BUSWD = H 16 bits) RDY (BUSWD = L 8 bits) RDY ((BUSWD = H 16 bits) DREQ, DACK RD, DREQ RD 300 Ratings min 20 -20 280 100 150 60 0 20 20 150 200 0 0 300 540 100 300 60 300 300 540 230 490 260 420 50 230 280 typ max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Application designs must take the RDY signal output delay into consideration if the RDY signal is used as the CPU bus wait signal. When the RDY signal is used, the "RD low-level width" and the "Corrected output RD width" values express the basic timing (excluding the wait time) settings for the CPU bus. If the RDY signal is not used, (that is, if no wait states are inserted) the value of the RD low-level width will be 280 ns (minimum). Electrical Characteristics at VDD = +2.7 to +3.6 V, within the allowable operating ranges Parameter Symbol VOH1 High-level output voltage VOH2 VOL1 Low-level output voltage VOL2 VOL3 High-level input current Low-level input current Input resistance Reference supply voltage output Bandpass filter center frequency -3 dB bandwidth Group delay Gain IIH1 IIH2 IIL Rmpx Vref Fc Fbw Dgd Gain ATT1 Stop band attenuation ATT2 ATT3 ATT4 Output off leakage current Hysteresis voltage Internal feedback resistor Current drain IOFF VHIS Rf IDD Conditions Io = 1 mA, BCK, FCK, BLOCK, FLOCK, CRC4, CLK16DATA Io = 2 mA, INT, RDY, DREQ, D0 to D15 Io = 1 mA, Pins for which VOH1 applies Io = 2 mA, Pins for which VOH2 applies Io = 1 mA, DO, INT VIN = 5.5 V, A0/CL, A1/CE, A2/DI, RST, STNBY VIN = VDDD, All input pins other than IIH1 VIN = VSSD, All input pins MPXIN - Vssa f = 100 kHz Vref, Vdda = 3 V FLOUT FLOUT FLOUT FLOUT - MPXIN f = 76 kHz FLOUT f = 50 kHz FLOUT f = 100 kHz FLOUT f = 30 kHz FLOUT f = 150 kHz V0 = VDDD, DO A0/CL, A1/CE, A2/DI, A3, CS, RD, WR, DACK, IOCNT1, IOCNT2, RST, STNBY XIN, XOUT 0.1 VDDD 1.0 12 20 25 15 50 50 1.0 -7.5 20 50 1.5 76.0 19.0 +7.5 Ratings min VDD - 0.4 VDD - 0.4 0.4 0.4 0.4 1.0 1.0 -1.0 typ max Unit V V V V V A A A k V kHz kHz s dB dB dB dB dB A V M mA No. 6871-3/29 LC72714W Block Diagram BLOCK FLOCK CLK16 DATA BCK Vddd Vssd 1T delay LPF Clock regeneration STNBY RST XOUT XIN Vref MPXIN Anti-aliasing filter 76kHz BPF (SCF) Vdda Vref Vssa 7.2MHz LPF 2T delay MSK correction circuit Synchronization regeneration FCK Timing control Error correction: layer 2 CRC PN decoding Data Address VICS processing Memory array Output control (CPU interface) and layer 4 CRC detection circuit CRC4 IOCNT1 IOCNT2 D0 to D15 A0/CL A1/CE A2/DI A3 DO FLOUT CIN DREQ DACK CS RD WR RDY INT SP VREF Pin Assignment BUSWD STNBY A1/CE A0/CL A2/DI Vssd Vddd RST WR INT DO RD NC CS SP A3 49 TIN NC Vssa Vref MPXIN Vdda FLOUT CIN NC TPC1 TPC2 TEST TOSEL1 TOSEL2 Vssd XIN 64 1 IOCNT1 Vssd DREQ DACK Vddd XOUT Vddd IOCNT2 CLK16 DATA FLOCK BLOCK CRC4 RDY FCK BCK 16 32 D15 D14 D13 D12 D11 D10 D9 LC72714W D8 D7 D6 D5 D4 D3 D2 D1 D0 (Top view) BUSWD TIN No. 6871-4/29 LC72714W Pin Functions Pin No. 3 4 13 38 39 40 41 42 43 44 46 45 47 48 60 58 59 61 62 49 5 6 9 10 7 8 11 33 12 16 Pin IOCNT1 IOCNT2 DACK WR RD A0/CL A1/CE A2/DI A3 CS RST STNBY SP BUSWD TEST TPC1 TPC2 TOSEL1 TOSEL2 TIN CLK16 DATA FCK BCK FLOCK BLOCK CRC4 INT DREQ RDY Data bus I/O control 1 (SP = Function low)*1 I/O Pin circuit Data bus I/O control 2 (SP = low)*1 DMA acknowledge (SP = low)*1 Write control signal (SP = low)*1 Read control signal (SP = low)*1 Address input 0 (SP = low) CCB CL input (SP = low) 1 (SP = low) CCB CE input (SP = low) 2 (SP = low) CCB DI input (SP = low) 3 (SP = low)*1 Chip select input (SP = L)*1 System reset input (negative logic) Standby mode (positive logic) SP = low: parallel, SP = high: serial BUSWD = low: 8 bits, BUSWD = high: 16 bits The test pin must be connected to the digital system ground (VSS). Must be connected to the digital system power supply (VDD) or ground (VSS) in normal operation. As above As above As above As above Clock regeneration monitor Demodulated data monitor Frame start signal output Block start signal output Outputs a high level during frame synchronization Outputs a high level during block synchronization Level 4 CRC detection result output External CPU interrupt request output DMA request signal Read ready signal Data bus Output Input Input 17 to 24 D0 to D7 The bus width can be set to be either 8 bits or 16 bits by the BUSWD pin (pin 48). For data input, only the lower 8 bits (D0 to D7) are valid. *3 I/O 25 to 32 D8 to D15 Data bus (in 16-bit mode) These pins are held in the output off state when BUSWD is low. Output 64 1 XIN XOUT Connections for the system clock crystal oscillator circuit. The XIN pin can also be used as an external clock signal input. I/O 53 MPXIN Baseband (multiplex) signal input Input 55 FLOUT Subcarrier output (76 kHz bandpass filter output) Output + - Continued on next page. No. 6871-5/29 LC72714W Continued from preceding page. Pin No. Pin Function I/O Pin circuit + 56 CIN Subcarrier input (comparator input) Input - Vref Vdda 52 VREF Reference voltage output (Vdda/2) Output Vssa 36 DO CCB serial interface data output Output 37 50 57 54 51 2, 15, 34 14, 35, 63 VDDA VSSA VDDD VSSD Analog system power supply Analog system ground Digital system power supply (+2.7 V to +3.6 V) Digital system ground -- -- -- -- NC This pin must be left open Notes: 1. This pin must be connected to VDDD or VSSD if the IC is used in serial interface mode (when SP is high). 2. A capacitor of at least 2000 pF must be inserted between VDDD and VSSD. 3. When used in the SP = high mode (as set by the serial interface), the D0 to D7 data bus lines must be connected to either VDDD or VSSD. Control Registers This IC includes both registers that can be read and registers that can be written. These registers can be accessed using either the serial interface (CCB) or the parallel interface. The SP pin switches between these interfaces. The initial values of the write registers are the data loaded into internal registers when a reset signal (RST) is received. These values are recommended values that do not need to be changed during normal operation. If the parallel interface is used, applications must hold the address fixed at 00H when reading out data to which error correction has been applied. If the CCB interface is used, the application needs only to specify the CCB address (#FB). The address 00H is an invalid address for writing. The addresses other than those specified below are control addresses particular to the IC. Applications must not specify those addresses. Address 1 2 3 4 5 6 Register BIC SYNCB SYNCF CTL1 CTL2 CRC4 Function Number of allowable BIC errors Block synchronization: error protection count Frame synchronization: error protection count Control register 1 Control register 2 Layer 4 CRC register R/W W W W W W W Address 1 2 Register STAT BLNO Status register Block number register Function R/W R R No. 6871-6/29 LC72714W Number of Allowable BIC Errors Address 01H Register BIC R/W W Initial value 22H BIT7 BIT6 BIT5 BIT4 (LSB) BIT3 BIT2 BIT1 BIT0 (LSB) Back protection Forward protection The synchronization circuit in this IC operates by recognizing a 16-bit BIC code. The number of allowable errors is the number of incorrect bits allowed in those 16 bits. This data sets up separate values for forward protection mode (when synchronized) and for back protection mode (when not synchronized). The default value is to allow 2 incorrect bits in both forward and back modes. If the block synchronization discrimination output (BLOCK) is used for discriminating whether or not FM multiplex data is present, we recommend setting the back protection mode BIC allowable error count to 1 or 0. Block Synchronization: Error Protection Count Address 02H Register SYNCB R/W W Initial value 17H BIT7 BIT6 BIT5 BIT4 (LSB) BIT3 BIT2 BIT1 BIT0 (LSB) Back protection Forward protection The synchronization protection count can be set separately for both forward and back protection. The count conditions for the protection counts are as follows. * Back protection mode (not synchronized: BLOCK = low) If the timing of the IC internal synchronization free-running counter matches the timing of the received BIC, the protection count is incremented by 1. Contrarily, if the timings of the IC internal counter and the received BIC do not match, the protection counter is cleared to 0. The timing of the count is the timing of the IC internal counter. * Forward protection mode (synchronized: BLOCK = high) In reverse to the back protection mode, if the timing of the IC internal free-running counter does not match the detection timing of the received BIC, the protection counter is incremented, and if the timings match, the protection counter is cleared to 0. Figure 1 shows the states of the protection counter for the cases where the forward and back protection counts are both 3. This IC defines the value of the protection counter to be 1 at the point that a match or a discrepancy occures between the IC internal timing and the timing of the received BIC. For example, when the value of the back protection count is 2, the IC internal timing and the timing of the received BIC will have matched two times consecutively. If the protection data is set to new values, for example if the protection counts are set to 3 as assumed in figure 1, applications must send values which are 1 less than the intended value; in this case 22H. Similarly, if the value is set to 00H, the protection counts will, by definition, be set to 1 for both the forward and back directions. However, note that the resulting operation will be equivalent to there being no protection circuit. The default values are 8 for the forward protection count and 2 for the back protection count. If the block synchronization output (BLOCK) is used for discriminating whether or not FM multiplex data is present, we recommend setting the block synchronization back protection count to a value that is more strict than the default value. (That is, we recommend replacing the default value of 2 with a value of 3 or higher.) BIC Received data 1 2 3 0 1 0 Reset Synchronization counter BIC position 1 2 3 Block * Assumes that the forward and back protection counts are 3. Figure 1 Block Synchronization Protection Operation (Forward Back Forward) No. 6871-7/29 LC72714W Frame Synchronization: Error Protection Count Address 03H Register SYNCF R/W W Initial value 17H BIT7 BIT6 BIT5 BIT4 (LSB) BIT3 BIT2 BIT1 BIT0 (LSB) Back protection Forward protection This IC detects the BIC characteristic inflection points which occur at four places in a single frame, and increments or decrements a protection counter depending on whether or not they match the IC internal frame synchronization timing counter. As is the case with the block synchronization error protection value, applications must set these to values one less than the desired protection count. The default values are 8 for the frame synchronization forward protection count and 2 for the back protection count. Control Register 1 Address 04H Register CTL1 R/W W Initial value 00H BIT7 BIT6 BIT5 BIT4 BIT3 EC_STOP BIT2 VEC_HALT BIT1 * BIT0 * CRC4_RST DO_MOVE INT_MOVE SYNC_RST *: BIT0 and BIT1 are unused. * VEC_HALT 0: Vertical correction and the second horizontal correction processing are performed. (default) 1: Vertical correction and the second horizontal correction processing are not performed. All IC operations related to vertical correction and the second horizontal correction are stopped by setting this flag. Note that in data output, only data to which the first horizontal correction has been applied will be output. * EC_STOP 0: All functions operate. (default) 1: Only the MSK detection circuit and the synchronization regeneration circuit operate. This flag stops all operations relating to error correction (including RAM access), data output, and other operations. While all IC operations are stopped in standby mode, MSK demodulation, the synchronization circuit, the serial data input circuit, and the layer 4 CRC circuit continue to operate in this mode. * SYNC_RST 0: (default) 1: Resets just the synchronization regeneration circuit. Clears the synchronization status and the synchronization protection status in the synchronization circuit block, and sets the circuit to the unsynchronized state. This allows the circuit to quickly pull in to frame synchronization when the frame synchronization is incorrect for the new reception data following tuning, when the radio has been tuned to a new station. While this flag is used for synchronization related sections of the system, it does not initialize the registers that set the number of allowable BIC errors, the block synchronization forward and back protection counts, and the frame synchronization forward and back protection counts. Also note that during a synchronization block reset, the INT signal is not output and the DO pin outputs a high level (high-impedance). This flag is not automatically reset to 0. Applications must send a 0 value after setting this flag. * INT_MOVE 0: Data is only output when error correction has completed, layer 2 CRC has completed, and the data was received with the circuit synchronized. (default) 1: All data is output. (Operation is identical to that of the LC72700E.) In the default state, this IC only outputs data that has been fully error corrected and that was received in both block and frame synchronization. (This also includes the layer 2 CRC check.) To acquire all data as provided by the LC72700, applications must set both this flag and the VEC_OUT (BIT2) flag in control register 2 as described below. * DO_MOVE (Valid only when SP is high.) 0: The high state (high impedance) is held at all times other than when data is being output. (default) 1: Operate identically to the LC72700 when changes are linked to the INT signal, i.e. when both INT_MOVE and VEC_OUT are set to 1. * CRC4_RST 0: (default) 1:Reset the layer 4 CRC detection circuit. This flag is not automatically reset to 0. Applications must send a 0 value after setting this flag. No. 6871-8/29 LC72714W Control Register 2 Address 05H Register CTL2 R/W W Initial value 00H BIT7 SUBBLK BIT6 BLK_RST BIT5 DACK BIT4 DREQ BIT3 RDY BIT2 VEC_OUT BIT1 DMA_RD BIT0 DMA * DMA (Valid only when SP is low.) 0: Do not use DMA transfer for readout of post-error correction data. (default) 1: Use DMA transfer for readout of post-error correction data. * DMA_RD (Valid only when SP is low.) 0: Use the RD signal as the DMA transfer read control signal. (default) 1: Use the DACK signal as the DMA transfer read control signal. * VEC_OUT 0: Do not perform post-horizontal correction output when vertical correction processing is not performed. (default) 1: Output all data, even when vertical correction processing is not performed. (Operation identical to that of the LC72700) When this flag is set and a frame of data with absolutely no errors is received, data that is completely identical to the corresponding post-horizontal correction data is output with the timing of the output of post-vertical correction data, even if vertical correction is not performed. This flag must be set to create interface specifications identical to those of the LC72700. * RDY (Valid only when SP is low.) 0: The RDY output is issued with timing 1. (default) 1: The RDY output is issued with timing 2. * DREQ (Valid only when SP is low.) 0: Negative logic is used for the polarity of the DREQ signal. (default) 1: Positive logic is used for the polarity of the DREQ signal. * DACK (Valid only when SP is low.) 0: Negative logic is used for the polarity of the DACK signal. (default) 1: Positive logic is used for the polarity of the DACK signal. * BLK_RST 0: (default) 1: Resets the block synchronization circuit only. Sets the block synchronization status to unsynchronized and clears the block synchronization protection counter. However, note that this has no effect on the frame synchronization functions. Also note that during a synchronization block reset, the INT signal is not output and the DO pin outputs a high level (high-impedance). This flag is not automatically reset to 0. Applications must send a 0 value after setting this flag. * SUBBLK 0: Normal status. (default) 1: Set to 1 when a substation (for example a dGPS station during VICS reception) is temporarily received. The SUBBLK and BLK_RST flags are mainly used when receiving and processing VICS data and dGPS data at the same time. (See page 28.) RD DATn Valid output RDY Timing1 RDY Timing2 RDY Signal Output Timing No. 6871-9/29 LC72714W Layer 4 CRC Register Address 06H Register CRC4 R/W W Initial value 00H BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 (LSB) This is the data group write register used for the layer 4 CRC check. It is used only when the parallel interface is used. Applications should specify the dedicated CCB address when using the serial interface. Status Register Address 01H Register STAT R/W R Initial value -- BIT7 VH BIT6 BLK BIT5 FRM BIT4 ERR BIT3 PRI BIT2 HEAD BIT1 CRC4 BIT0 * *: BIT0 is unused. * VH 0: Indicates data for which only horizontal correction was performed. 1: Indicates data for which after horizontal correction, vertical and then second horizontal correction were performed as well. * BLK 0: Indicates data that was received with block synchronization unsynchronized. 1: Indicates data that was received with block synchronization synchronized. * FRM 0: Indicates data that was received with frame synchronization unsynchronized. 1: Indicates data that was received with frame synchronization synchronized. * ERR 0: Indicates data for which error correction completed and no errors were detected in the level 2 CRC check. 1: Indicates data for which error correction was not possible or for which errors were detected in the level 2 CRC check. * PRI 0: Indicates data that was inferred to be data block data by the frame synchronization circuit. 1: Indicates data that was inferred to be parity block data by the frame synchronization circuit. * HEAD 0: 1: Indicates data that was inferred to be in the frame head block by the frame synchronization circuit. This flag is valid only when VH is 0. * CRC4 0: Indicates that the layer 4 CRC detection circuit division registers were not all zeros. 1: Indicates that the layer 4 CRC detection circuit division registers were all zeros, i.e. that there were no errors. The result at the point immediately prior to register readout is loaded into this flag. Block Number Register Address 02H Register BLNO R/W R Initial value -- BIT7 BLN7 BIT6 BLN6 BIT5 BLN5 BIT4 BLN4 BIT3 BLN3 BIT2 BLN2 BIT1 BLN1 BIT0 BLN0 Indicates the block number or the parity block number of the output data. A single frame consists of data blocks numbered 0 to 189 and parity blocks numbered 0 to 81. Output following vertical correction does not include parity block data. The value of the block number register is undefined if VEC_HALT (bit 2 in control register 1) is set to 1. No. 6871-10/29 LC72714W Data Update Timing for Read Registers The data in the two read registers (the status register at address 01H and the block number register at address 02H) is updated in the 1 ms interval between 1 ms prior to the output of the interrupt control signal (INT) and a point immediately before the INT output. In normal processing, when an interrupt occurs, the application will first determine the nature of the data packet that will be output by the current interrupt signal by reading out the status register, and determine if it is necessary to read out that data. For example, if error correction failed and the erroneous data is not required, the application should simply wait for the next interrupt. If the CCB interface is used, the application reads out the data from CCB address #FB, and determines the status from the additional 16 bits of data. It then either reads out the following data or sets the CE signal low to cancel the readout. Applications can also read out data asynchronously with respect to the interrupt signal. In this case, the application checks the current reception status by reading out the status register and checking bit 6 (data received in the block synchronized state) and bit 5 (data received in the frame synchronized state). In this case, using data for which bit 7 (VH) is 0 provides superior real time characteristics. CPU Interface Timing tWRDL1, tWRDL2 tCYRD A0 to A3 CS tSARD tHARD RD tDRDY RDY tWRDY tRDH DATn Valid output * tHARD stipulates the earliest timing for A0 to A3 and CS. No. 6871-11/29 LC72714W * Register Write Timing tWWRL tCYWR A0 to A3 CS tSAWR WR tHAWR tWDH DATn * Post-Correction Data Read Timing tCYRD *: A0 to A3: When post-correction data is read, A0 to A3 will be held fixed at 0. tWDRD1, tWDRD2 A0 to A3 CS tSARD tDRDY RD tWDRDY RDY tRDH DATn Valid output Valid output No. 6871-12/29 LC72714W * Post-Correction Data Read Timing (DMA) tDREQ tWRDM DREQ DACK RD A0 to A3 CS tRDH DATn tCYDM *: A0 to A3: When post-correction data is read, A0 to A3 will be held fixed at 0. *: DREQ and DACK: The polarity of these signals can be set. *: Applications can select whether the DR or DACK signal is used for readout. Layer 4 CRC Detection Circuit Data block (176 bits) Post-error correction data Structure of a Single Data Packet (Total length: 272 bits. BIC is not included.) Layer 2 CRC (14 bits) Parity (82 bits) *: This data is not output. No. 6871-13/29 LC72714W CPU Interface I/O mode Input Output Input Output CCB address B0 0 1 0 1 B1 1 1 0 0 B2 0 0 1 1 B3 1 1 1 1 A0 1 1 1 1 A1 1 1 1 1 A2 1 1 1 1 A3 1 1 1 1 16-bit control data input Data corresponding to the number of clock (CL) cycles is output Data input mode for the layer 4 CRC detection circuit (8-bit units) Register output only Item Data input (Register write) Data is stored in an IC internal register. The CCB address #FA and 16 bits of data (DI0 to DI15) are input to the DI pin. The bits are assigned as follows. Although DI12 to DI15 are unused data, arbitrary values must be provided to complete a full 16 bits of data. See the "Control Register" section earlier in this document for details on the register contents and addresses. Details on writing to the layer 4 CRC check register are described later in this document. (The CCB address #FC is used for this function.) DI0 BIT0 (LSB) DI1 BIT1 DI2 BIT2 DI3 BIT3 DI4 BIT4 DI5 BIT5 DI6 BIT6 DI7 BIT7 (MSB) DI8 BIT0 DI9 BIT1 DI10 BIT2 DI11 BIT3 DI12 to DI15 Unused data Input data (8 bits) Register address tEL CE tCH CL tSU DI B0 tHD B1 B2 B3 A0 A1 A2 A3 tCL tES tEH DI0 DI1 DI2 DI13 DI14 DI15 tLC Internal data latch operation Data Output (Post-correction data output) The IC outputs packet data to which error correction processing has bee applied. The application inputs the CCB address #FB to DI. tEL CE tCH CL tSU DI B0 tHD B1 B2 B3 A0 A1 A2 A3 tDDO DO DO0 DO1 DO2 DO285 DO286 DO287 tCL tES *: The DO pin is normally left open. Since the DO pin is an n-channel open-drain output, the data change time from a low-level output to a high-level output differs due to the pull-up resistor. No. 6871-14/29 LC72714W Structure of the Post-Correction Output Data STAT (8 bits) DO0 to DO7 BLNO (8 bits) DO8 to DO15 Data section (176 bits) Post-error correction data DO16 to DO191 Layer 2 CRC (14 bits) DO192 to DO205 Parity (82 bits) DO206 to DO287 Layer 4 CRC Check Circuit tEL CE tCH CL tSU DI B0 tHD B1 B2 B3 A0 A1 A2 A3 CR0 CR1 CR2 N-2 N-1 N tCRC CRC4 pin output Note: The number of items, N, refers to the number of 8-bit items. tCL tEH tES CRC4 pin output after N items have been transferred. Register Output The IC internal status and block number registers are special-purpose registers that can be read out by applications. (See the discussion of the read register data update timing on page 12.) The application inputs the CCB address #FD to DI. The status register data is output first followed by the block number register data. tEL CE tCH CL tSU DI B0 tHD B1 B2 B3 A0 A1 A2 A3 tCL tES tDDO DO ST0 ST1 ST2 BLN5 BLN6 BLN7 No. 6871-15/29 LC72714W Notes on Operation during Resets and in Standby Mode Reset Signal The reset operation is executed when the supply voltage (VDD) rises above 2.5 V (2.5 V in the LC72710LW) and the RST pin input level is held at or below VIL for 300 ns or longer. (See the figure below.) When power is first applied, or when power is removed and applied again, always apply a reset before using this IC. VDD voltage 2.5 V RST VIH VIL (0.3 VDD) 300 ns (min) Pin States during Reset Low level:CLK16 (5), DATA (6), FLOCK (7), BLOCK (8), FCK (9), BCK (10) High level: INT (33), RDY (16), CRC4 (11), DREQ (12) Open: D0 (17) to D15 (32), DO (36) Reset Operating Range The states of the output pins as the result of a reset signal are stipulated in the "Pin States during Reset" item above. The IC internal flip-flops are all reset. While the shift registers used for delay are also reset, the memory array is not influenced by this operation. However, since memory is not refreshed, data cannot be retained. The crystal oscillator circuit is not stopped. Post-Reset Data Input After a reset operation has completed, if at least one clock cycle (about 278 ns when the IC's main clock is 3.6 MHz) elapses, the register write circuit will be functional. (That is, the IC can accept data.) Notes on Standby Mode The IC is set to standby mode by applying a high level to the STNBY pin. Since all IC operations are stopped in this mode, the state is essentially equivalent to removing power from the IC. (Note that after clearing standby mode, applications must wait the oscillator stabilization time before using the IC.) The pin output states during standby mode are the same as those states during a reset as described above. The internal VICS registers are cleared and the status flag values are not retained. Output Conditions for Post-Error Correction Output (Default Mode) (1) For each block (272 bits) of received data, the IC applies (272, 190) code error correction and a layer 2 CRC error check. After the error correction has completed, the IC prepares to transfer the data to the CPU and outputs an interrupt signal from the INT pin. This is referred to as horizontal correction output. (2) Note that under the default operating conditions, this interrupt signal is not output unless the corresponding output data meets the following three conditions. * Error correction completed correctly and no errors were discovered in the layer 2 CRC check. * The data was received in both block and frame synchronization. * The data is packet data. (3) If the data could not be corrected in horizontal correction, product code correction is performed in frame units and a second horizontal correction operation is performed for this data that could not be corrected by the first horizontal correction. This sequence of operations is called vertical correction. The output conditions for data that can be acquired after vertical correction are as follows. * The data that could not be corrected by horizontal correction only, but that was corrected by vertical correction. * The data is packet data. Continued on next page. No. 6871-16/29 LC72714W Continued from preceding page. This means that data that was fully corrected by horizontal correction is not output. Also, packet data that could not be corrected by either horizontal correction or vertical correction is not output. Furthermore, post-vertical correction parity packet data is also not output. (4) Applications can clear the INT signal selection conditions described in (2) and (3) above by setting bit 5 (INT_MOVE) in the control register. (5) Vertical correction is performed when all of the packet data in a frame is received in frame synchronization and furthermore when it was not possible to correct all of the packet (block) data with horizontal correction. Vertical correction is not performed if one frame of data with no errors was received or the receiver was not in frame synchronization during reception. To prevent incorrect correction, error correction using vertical correction is not performed for packets error correction using horizontal correction fully completed and for packets that had no errors. (6) Under the default settings, if vertical correction is not performed, the corresponding post-vertical correction output is not output. Applications can specify the post-vertical correction data to be output regardless of whether or not vertical correction is performed by setting bit 2 (VEC_OUT) in control register 2. Note 1. In this case, if data with absolutely no errors is received, completely identical data will be output twice, once as horizontal correction output, and once as vertical correction output. This status is identical to the output status of the LC72700E. Note 2. Immediately after power is applied, undefined data that is, in principle, not required by applications, will be output as post-vertical correction data. CPU Interface Basic Limitations To save internal memory, this IC limits its output data buffer to the smallest size possible. Since the data received by the IC is written to memory continuously without interruption, the post-correction data in the output data buffer that should be read out may be overwritten by the following data if readout of the data is delayed. The output timing for post-correction data, both horizontal and vertical, is stipulated as follows for this IC. (1) When the IC completes preparation of the output data, it drops the INT pin to the low level as a transfer request. (2) During data output, there are periods when only horizontal data can be read out, and there are other periods when both horizontal data and vertical data can be read out in a time-division multiplexed manner. (3) Applications must complete the data transfer operation within 9 ms after the INT pin goes low. If only posthorizontal correction data is output, the data transfer may be performed within an 18 ms period. After the stipulated period, the next data will be written to the output buffer replacing the previous data, even if the CPU is reading out the data. (4) The amount of data that can be read for a single transfer request (INT) for each of the horizontal and vertical data is one block only. The post-vertical correction data is output in order starting with block number 1 after vertical correction processing completes. The parity block data is not output. 18 ms INT 1 ms Horizontal data only output Horizontal and vertical data output Horizontal data output period Period during which data retention is not guaranteed 68 s Horizontal data output period Vertical data output period 68 s Figure 2 External Interface - Basic Timing No. 6871-17/29 LC72714W Notes on Data Output Timing (Relationship with the received data) Figure 3 shows the timing relationship between the received data and the interrupt control signal (INT). However, the delay from the actual received signal due to demodulation operations in MSK demodulation blocks is ignored. Block synchronization is established by discriminating the BIC code. As shown in figure 3, the data for the nth packet can be output during reception of the following packet (number n+1). Figure 4 shows the output timing for post-vertical correction data. In vertical correction, the data for a single frame is stored in memory and the correction operation is performed if frame synchronization was established and it was not possible to correct all the packet data in horizontal correction. The timing with which vertical correction is started is the start of the frame. Horizontal correction is performed for each packet while packets 1 through 28 in the nth frame are being received, and this data is passed to the CPU interface. Vertical correction is performed for the data from the previous frame (frame n-1) in the unused time periods during that processing. The vertical correction data consists of 190 blocks that are output, and this data is output at the rate of one block for every block received, in order starting at the time the 29th packet (block) is received. Only data from the data blocks in the FM multiplex broadcast frame structure is output, and the last block (block 190) is output during reception of the 218th block. As indicated previously (page 18) packet data that was, for example, corrected completely by horizontal correction, is not output in the vertical correction output data. (The INT signal is not issued.) However, the order in which the horizontal output is produced is not speeded up by the amount of the packet data that is not output. For example, if data packets 1 to 100 were corrected by horizontal correction, output of the post-vertical correction packet data for packet 101 will not occur at the reception position of block number 29 in figure 4, but at the reception position for packet data number 129. Packet n data Packet n-1 Received data BIC Packet n+1 BIC 18 ms 300 ns max BCK 62.5 s 300 ns max INT 1 ms Output period for packet n+1 data 68 s Data cannot be guaranteed Packet n data output Figure 3 Received Data, Block Synchronization, and Data Output Timing Received block signal 271 BCK First frame 272 1 nth frame 2 3 28 29 30 31 218 219 220 62.5 s FCK 18 ms 1 INT 1 ms 18 ms 18 ms x 28 = 504 ms 9 ms 9 ms Output periods for post-vertical correction data from the prevoous frame. 2 189 190 Figure 4 Post-Vertical Correction Data Output Timing No. 6871-18/29 LC72714W CPU Connection Example LC72714W D0 to D7 (D0 to D15) CPU A0 to A3 WR RD CS INT RDY DREQ DACK IOCNT1 IOCNT2 BUSWD RST SP BUS-Width 8 bits PORT1 WR RD CS INT WAIT * DMA transfer mode I/O read/write operations are used for the normal register read and write operations. However, programmable wait states may need to be inserted, depending on the execution speeds. DMA processing is only used for readout of post-correction data. Applications can select whether RD or DACK is used as the DMA read control signal by setting a register. The default is to use the RD signal. The data bus width in DMA mode is always 8 bits. CPU DMA mode setting example (For reference only) SH Series: Transfer type: 2-cycle transfer Transfer mode: Single transfer mode V Series: Address mode: Dual address mode Bus mode: Cycle stealing mode The source side (the FM multiplex IC) address is fixed at 0. LC72714W CPU D0 to D7 A0 to A3 WR RD CS INT RDY DREQ DACK BUSWD IOCNT1 IOCNT2 RST SP BUS-Width 8 bits WR RD CS INT DREQ DACK PORT1 No. 6871-19/29 LC72714W * Data bus I/O control block The data bus (D0 to D15) can be controlled with two control signals: IOCNT1 and IOCNT2. These pins must be held low if unused. CS RD DACK IOCNT1 IOCNT2 Control register 2, bits 1 and 2 D0 to D15 CPU Connection example LC72714W A1/CE A0/CL A2/DI CPU PORT1 SCK (*) TX (*) DO INT RX (*) PORT2 (INT) RST PORT3 SP * SCK, TX, and RX are the CPU serial interface channel. Normally, I/O port pins may be used for these lines. * The resistance of the DO pin pull-up resistor must be selected according to the transfer clock speed. No. 6871-20/29 LC72714W Control Program Compatibility This IC allows the majority of the control software used to be compatible with Sanyo's other FM multiplex ICs, in particular, the LC72700E, LC72705E, LC72706E, LC72708E, and LC72709E(W). However, the following aspects of the control software require modification. * Values of the register addresses The addresses of the allowable BIC error count, synchronization error protection count, control registers, the layer 4 CRC register, and other registers have been modified. The CCB address for serial I/O over a CCB bus has not been changed. * INT signal output timing The INT signal output timing for data output is as follows. A circle ("O") indicates that INT is output, and a cross ("X") indicates that the signal is not output. Control register 1 bit 5, INT_MOVE L H Control register 2 bit 2, VEC_OUT L H Horizontal correction output Operational overview Correct data q q Incorrect data x q Parity Vertical correction output Correct data q *1 q *2 NG x q Item Default value Combination 1 Operation identical to that of the LC72705/06E and LC72708/09E(W) Operation identical to that of the LC72700E All data is output The output data selection conditions are cleared, but there is no vertical correction output when vertical correction is not performed The output data selection conditions are retained, but all of the vertical correction output is output x q Combination 2 H L q q q q *3 q Combination 3 L H q x x q q Notes:1. Data for which horizontal correction failed, but for which vertical correction succeeded is output. 2. All data is output. 3. If there is data for which horizontal correction failed, the post-vertical correction data for that data is output, regardless of whether or not vertical correction succeeded. (If the IC performs vertical correction, post-vertical correction data will be output.) Notes on Output Data Selection after Tuning (Reference) When building an FM multiplex reception system, a tuning system is an absolute necessity. However, if it is unacceptable for the IC to output data from the old station after tuning to a new station, the application must perform the following processing. (1) At the same time as tuning a new station, the application must set bit 4 (SYNC_RST) in control register 1 to set the synchronization circuit to the unsynchronized state. (2) Under the default settings, after the synchronization reset applications must acquire data according to the issued INT signal. The post-vertical correction output is not provided by the IC until frame synchronization has been established for the new station after tuning and the first vertical correction operation has been performed. (3) If bit 2 (VEC_OUT) in control register 2 has been enabled, applications must not use the post-vertical correction output (data for which bit 7 in the status register is high) until frame synchronization has been reestablished. This IC performs the portion of the DARC FM multiplex processing through layer 2 error correction without requiring any special control operations. The IC itself cannot determine if the contents of the received data have changed or if a new station has been tuned. This means that applications must use the procedure described above for this IC not to output old data and only output the new data. Another point is that in IC synchronization, although it is rare for the old station and the new station to be frame synchronized, applications need to perform the processing in item 1 above to cancel frame synchronization forward protection period. No. 6871-21/29 LC72714W Sample Data Acquisition Flowchart Note: The figure below is for allocation of received data at the layer 3 level. This documentation is present as an example for reference purposes only of FM multiplex data acquisition processing by the system CPU. Its operation is not guaranteed. INT Status acquisition Correction complete? ** This discrimination is not required with the default settings. (No INT signal is issued.) Synchronized? Read in the postcorrection data (22 bytes) Was this post-horizontal correction data? YES Prefix discrimination Prefix discrimination Is the data group complete? Is the data group complete? YES YES Is the decoding identifier 1? YES Start decoding and presentation processing Layer 4 CRC check Start decoding and presentation processing Layer 4 CRC check END No. 6871-22/29 LC72714W Prefix discrimination YES Is this the data group for the first reception? Allocate a storage area the size of the data group. YES Update? Update the data in the existing data storage area. NO Resend? Check the correctness of the received data packet. YES NO Is the data group complete? Store in the corresponding data group storage area. YES End Additional Notes In addition to the above processing, processing required for layer 3 (data group) level processing includes "deletion of inappropriate data." Although rare, in certain cases the IC will send inappropriate packet data that does not belong to any data group currently being broadcast. The following three points are possible reasons for this occurring. (1) The IC frame synchronization circuit generates an incorrect synchronization state, and the IC incorrectly outputs parity packet data as normal packet data. This can occur when the back protection count is less rigorous (2 or lower), or during weak field reception. (2) While extremely rare, incorrect correction can occur. (This almost never happens.) (3) Noise entering the data transfer lines between the FMD IC and the CPU within the end product set. Inappropriate packet data that occurs for these reasons and does not belong to any data group, will not be updated, and will remain in the program storage memory indefinitely. If the application does not include a routine that searches for and deletes inappropriate data, program storage memory will overflow at some point. Also, applications should perform a layer 4 CRC check after data group completion and before program display. There are situations where the layer 4 CRC data is not present in the additional information. We recommend recognizing such cases by judging in software at the layer 5 (segment) level whether or not the corresponding packet data is valid as an addition information packet. No. 6871-23/29 LC72714W Notes on Simultaneous Reception of VICS and dGPS Data Currently, VICS service data and dGPS service data are broadcast from different stations. Since the amount of the dGPS data is small, 2 packets per frame, it is possible to receive both VICS data and dGPS data with a single tuner by controlling the tuning of the receiver during the reception of mainly VICS data. During this operation, only the results of horizontal error correction are used for dGPS data, and the VICS data that is missing due to the reception of dGPS data is decoded (recovered) by using vertical direction error correction. (Caution: If there are any bad packets other than the missing data, it may not be possible to recover the data.) This IC includes functions that allow simultaneous acquisition of both VICS and dGPS data by controlling the tuning of a single tuner. The following section describes the procedure for data reception using this function. * Notes on block and frame synchronization circuit operation Normally, if the block synchronization system issues an incorrect synchronization, the count timing of the frame synchronization counter, which is based on the block synchronization, changes along with that error. If this state continues for an extended period, the frame synchronization circuit will take this new block synchronization timing to be correct, and discard the timing based on the original station A. This is the situation that occurs during normal tuning. That is, after the time for the frame synchronization forward protection count has passed, frame synchronization is lost, and then after the time for the frame synchronization back protection count has passed, synchronization is established with a synchronization timing that is different from that of station A, which had been the prior situation. Also, even if there is a block synchronization error for a short period, the temporary change in the block period can cause a timing discrepancy in the frame synchronization counter, which is based on the block synchronization. VICS data dGPS data Tuning One frame Frame phase difference Missing data Figure 5 VICS and dGPS Data This IC includes a compensation function to handle temporary incorrect synchronization in the block synchronization circuit. What we are referring to as temporary incorrect synchronization in the block synchronization circuit is the phenomenon shown in figure 6. Here, while the system is mainly receiving station A, the signal-to-noise ratio is degraded for some reason and the circuit synchronizes with a timing that does not actually exist. After that, the circuit resynchronizes with the block synchronization timing for the original station A due to, for example, improved reception conditions. Even if such a condition occurs, the functions included in this IC allow it to actually acquire all the data that can be acquired and furthermore, the synchronization circuit will not disrupt those conditions. No. 6871-24/29 LC72714W In figure 6, it is also possible to see the period timing that caused the incorrect synchronization with a timing other than that for station A to be a sub-reception station completely separate from station A, referred to here as station B. This IC is thus able, in this manner, to acquire data from both stations when the tuning is switched between station A and station B without any special control operations. In this case, it is necessary for there to be temporary block synchronization with station B, and this allows us to apply this operation to the case of data reception for VICS data (main station A) and dGPS data (sub-station B). In figure 6, the temporarily received data for station B can be acquired as post-horizontal correction output data, which is a real-time output, and the station A data can be acquired as fully decoded data in the post-vertical correction data. Main reception station A Incorrectly synchronized station or Sub-reception station B Figure 6 Main Reception Station and Sub-Reception Station * Control method This section presents an example of a possible flow of control. First, the application detects the frame phase difference between the VICS station and the dGPS station, and then sets the tuning control start timing based on that phase difference. The frame synchronization forward protection count is set to at least 3, and the block synchronization back protection count is set to 2. Since BLK_RST, which only resets the block synchronization circuit, is used, there is no need to modify the block synchronization forward protection count. Note that these settings can be replaced by the default settings used by this IC. When the BLK_RST is cleared after tuning the dGPS station, the IC starts block synchronization pull in, and after the time corresponding to the block synchronization back protection count has passed, block synchronization with the dGPS station data will be established. The post-horizontal correction output data (data for which status bit 7 (VH) is 0) that is output from this point will be data received from the dGPS station. After acquiring the stipulated number of packets of data, the application sets BLK_RST valid again, and tunes back to the VICS station. If the dGPS station reception conditions are unluckily unfavorable, it will not be possible to establish block synchronization, or it may not be possible to acquire fully corrected packet data. However, even if such conditions occur, the receiver must tune back to the VICS station after receiving the stipulated number of packets of data. The reason is that if the receiver did not do so, it would become impossible to completely decode the data in vertical correction for the VICS station itself, which is the main station being received. Since the ability of vertical correction to correct burst errors is about 10 packets, this sequence of tuning and data acquisition operations must completed within 10 packets. If that condition is met, it will be possible to decode the VICS station data. However, this is only possible when there are no packets that cannot be corrected other than those missed during the sequence of the simultaneous reception processing. No. 6871-25/29 LC72714W VICS - dGPS Reception No Is the timing now that for dGPS reception? Yes Set the frame forward protection count to 3 or higher, set the block back protection count to 2, and set the allowable number of BIC errors to 1. Control register 2 bits 6 and 7 BLKRST 1 SUBBLK 1 Tune the dGPS station BLKRST 0 Acquire horizontal correction data (3 or 4 packets) BLKRST 1 Tune the VICS station BLKRST 0 SUBBLK 0 Continue with normal data reception processing. No. 6871-26/29 LC72714W Figure 7 shows the flow of the dGPS data reception sequence focusing on the block synchronization state. Block synchronization is immediately set to the unsynchronized state by BLK_RST, and the IC then reacquires block synchronization with the dGPS station. Of course, if the dGPS station reception conditions are unfavorable, time will pass without acquiring block synchronization. In the example shown in this figure, the period during which VICS station data cannot be acquired with horizontal correction processing is a 6-packet period. Since the ability of vertical correction to correct burst errors is about 10 packets, this example has a margin of about 4 packets. This margin can be applied to the period for establishing block synchronization with the dGPS station. That is, the best timing for tuning from the VICS station to the dGPS station is about 4 packet positions before the position of the packet that has dGPS data. Tuning the dGPS station BLK RST VICS station block period Missing data 1 Missing data 2 Missing data 3 Missing data 4 Tuning the VICS station BLK RST Missing data 5 Missing data 6 dGPS station block period Protection count: 1 Protection count: 2 dGPS data IC block synchronization Post-horizontal correction output INT signal OK VCKS data Bad data OK data OK dGPS data OK dGPS data Bad data Bad data Figure 7 VICS - dGPS Simultaneous Reception * Notes (1) The approach of using a single tuner for channel selection in the acquisition of both VICS and dGPS data, has certain disadvantages from the standpoint of complete acquisition of the VICS data. This is because the VICS station data transmitted while the tuner is tuned to the dGPS station will be handled as invalid data or bad packet data. While the inherent vertical error correction capability is 10 to 12 bits, if we subtract the number of incorrect VICS station packets during dGPS station reception, it is clear that this will seriously reduce the reliability of recovery based on vertical error correction of the VICS data. This point must be taken into consideration. (2) When using the control technique described above, the time allowed for dGPS data acquisition will be the time required for about 10 packets. We recommend using the following synchronization system settings in order to acquire the dGPS packet data within such a brief time. The reason the number of allowable BIC errors is changed to a more strict value is to reduce the occasions where incorrect BICs are checked. However, even with these settings, it may not be possible to lock synchronization with the set protection count if the reception conditions are poor. Default setting Number of allowed BIC errors (backward) 2 Block synchronization error protection count (backward) 1 Frame synchronization error protection count (forward) 7 Recommended setting 1 1 (The default value can be used) 3 or higher (The default value can be used) (3) Bit 7 in control register 2 (SUB BLK) must be set to 1 during dGPS data reception. If this flag is not set, decoding for the VICS data vertical correction may not complete. No. 6871-27/29 LC72714W Sample Application Circuit (CCB serial interface) CPU Interface STNBY A1/CE A0/CL A2/DI RST 5 k 3.3 F (*) Analog GND INT DO 49 32 331 FM composit 10 F 22 H (*) LC72714W 561 22 H (*) SQFP-64 64 1 16 16 pF 16 pF + - This application circuit example can be used without change with any of the following ICs. LC72710W, LC72710LW, LC72711W, LC72711LW, LC72713W, LC72714W *: The information in this document is an example only, and the values shown are not guaranteed for use in the design of mass produced products. Power supply pins Pins 14, 15, 34, and 35: DRAM power supply Pins 2 and 63: Digital system power supply Pins 51 and 54: Analog system power supply The RD, WR, CS, and DACK pins can also be handled by connecting them to ground. *: The capacitors and coils marked with an asterisk (*) are used to isolate the analog and digital power supplies. The technique used for separation shown here is presented for reference purposes, and may be modified if required. No. 6871-28/29 LC72714W * The DARC (Data Radio Channel) FM multiplex broadcast technology was developed by NHK (Japan Broadcasting Corporation). * DARC is a registered trademark of NHK Engineering Service (NHK-ES). * A separate contract with NHK-ES is required in advance for the manufacture and/or sale of electronic equipment that uses DARC technology. * The logo shown here can be displayed on electronic equipment that uses DARC technology. * Sanyo Electric Co., Ltd. has reported to NHK-ES the number of units and purchasers of ICs that use DARC technology shipped since October 1997. Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of September, 2001. Specifications and information herein are subject to change without notice. PS No. 6871-29/29 |
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